The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device capable of increasing storage capacitance and preventing leakage current and method of manufacturing the same.
Along with the recent progress in the semiconductor manufacturing technology, the demand for memory device has increased dramatically. Consequently, a memory device having higher capacitance per small dimension is required. Capacitance of the capacitor is increased by using an insulator having high dielectric constant or enlarging the surface area of a lower electrode. Those conventional capacitors have been made with tantalum-oxide (Ta2O5) layer having a dielectric constant higher than that of nitride-oxide (NO) layer, thereby forming the lower electrode having 3-Dimensional structure.
FIG. 1 is a cross-sectional view of a capacitor in a conventional semiconductor memory device. Referring to FIG. 1, a field oxide layer 11 is also formed at a predetermined portion of the substrate 10. A gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed by a known technique at a predetermined portion of a semiconductor substrate 10. A junction region 14 is formed on the semiconductor substrate 10 at each end of the gate electrode 13, thereby forming a MOS transistor. A first interlevel insulating layer 16 and a second interlevel insulating layer 18 are formed on the semiconductor substrate 10. A storage-node contact hole h is formed in the first and the second interlevel insulating layers 16, 18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed by a known technology with in the storage-node contact hole h to contact the exposed junction region 14. A HSG (hemi-spherical grain) layer 21 is formed on a surface of the lower electrode 20 in order to increase the surface area of the lower substrate 20. A Ta2O5 layer 23 is formed on the surface of the HSG layer 21. At this time, the Ta2O5 layer 23 is formed as follows. First, a surface of the HSG layer 21 is cleaned before the Ta2O5 layer 23 is formed, and then the RTN (rapid thermal nitridation) process is performed ex situ thereby forming a silicon-nitride layer 22 on the HSG layer 21. Next, a first Ta2O5 layer is formed at temperature of approximately 400-450xc2x0 C. with thickness of 53-57 xc3x85. Afterward, an annealing process is performed at low temperature, and then there is formed a second Ta2O5 layer with the same thickness and by the same process as in the first Ta2O5 layer. Annealing processes at low temperature and at high temperature are continued in series thereby forming a single Ta2O5 layer 23. An upper electrode 24 is deposited on upper portions of the Ta2O5 layer 23 and the second interlevel insulating layer 18, thereby completing the formation of a capacitor.
However, the conventional capacitor according to the above method using the Ta2O5 layer as a dielectric layer has the following problems.
First, a difference in the composition rate of Ta and O results since Ta2O5 generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms, are generated in the Ta2O5 layer. Since those vacancy atoms are oxygen vacancy, leakage current result. The amount of vacancy atoms in the dielectric layer can be controlled depending on the contents and the bond strength of components in the Ta2O5 layer; however, it is difficult to eliminate them completely.
In order to stabilize the unstable stoichiometry of Ta2O5, the Ta2O5 layer is oxidized so as to remove the substitutional Ta atoms in the Ta2O5 layer. However, when the layer is oxidized, an oxide layer having low dielectric constant is formed at an interface between the Ta2O5 layer and the lower electrode or the Ta2O5 layer and the upper electrode since Ta2O5 easily oxidizes with the lower and the upper electrode made of polysilicon or TiN., thereby degrading the homogeneity of the interface.
Further, due to the reaction between an organic substance such as Ta(OC2H5)5 used as a precursor and O2 (or N2O) gas as a reaction gas, impurities result, such as carbon atoms C, carbon compounds(CH4, C2H4) and H2O in the Ta2O5 layer. These impurities increase leakage current in the capacitor and degrade the dielectric characteristics of the Ta2O5 layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.
Moreover, the use of the Ta2O5 layer as a dielectric layer generates extra ex-situ steps, one before formation of Ta2O5 layer and one after the cleaning step. Also, two thermal processes, at low and high temperatures, preferably is performed after the Ta2O5 layer has been formed. Therefore, forming a dielectric layer with Ta2O5 using the conventional method is cumbersome.
Accordingly, it is one object of the present invention to provide a capacitor for semiconductor device capable of obtaining a great capacitance by providing a dielectric layer having low leakage current and high dielectric constant.
Furthermore, the other object of the present invention is to provide a method of manufacturing capacitor for semiconductor device capable of simplifying its manufacturing process.
According to one aspect of the present invention, a capacitor for semiconductor memory device includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline TaxOyNz layer, and the total of x, y, and z in the crystalline TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.
In another aspect of the present invention, a method of manufacturing a capacitor on a semiconductor substrate includes the steps of: forming a lower electrode on the semiconductor substrate; depositing an amorphous TaxOyN2 layer as a dielectric layer on the lower electrode; crystallizing the amorphous TaxOyNz layer; and forming an upper electrode on the crystalline TaxOyNz layer, wherein the total of x, y and z in the TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.
Still other aspect of the present invention, a method of manufacturing a capacitor on a semiconductor substrate includes the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent a natural oxide layer generation on the surface of the lower electrode; depositing an amorphous TaxOyNz layer as a dielectric layer on the lower electrode; crystallizing the amorphous TaxOyNz layer; and forming an upper electrode on the crystalline TaxOyNz layer, wherein the total of x, y and z in the TaxOyNz layer is 1, y is 0.3 to 0.5, and z is 0.1 to 0.3, and the amorphous TaxOyNz layer is obtained by supplying Ta chemical vapor obtained from a precursor, O2 gas and NH3 gas with pressure of 0.1 to 100 Torr at temperature of 300 to 600xc2x0 C. in an LPCVD chamber and by a surface chemical reaction thereof.
Herein, O2 gas is supplied by 50 to 150 sccm and NH3 is supplied by 30 to 70 sccm.